1. Field
The following description relates to a semiconductor device, and to a semiconductor device configured to reduce gate-drain capacitance (Cgd), in an edge region in which an interconnection is formed to transfer a voltage to a plurality of trench transistors that are formed in an active region, by further forming a shield electrode that is connected with a source power, at or below a portion of a gate electrode of the edge region.
2. Description of Related Art
Channels of metal-oxide-semiconductor (MOS) transistors are mainly used to implement high voltage semiconductor devices. In such high voltage semiconductor devices, double diffused metal-oxide-semiconductor field-effect (DMOS) transistors are formed horizontal to a surface of substrate. However, due to recent reduction of a design rule of a semiconductor device, trench MOS transistors may be used to implement high voltage semiconductor devices. Such high voltage MOS transistors having vertical channels that are easily integrated to a high degree. In the trench MOS transistor, a drain is arranged at a bottom side (or a back side) of a substrate, and a source is arranged on an upper side (or a front side) of a substrate. A gate is arranged inside trench that is dented into the substrate surface, and the current flows along a side wall of the trench, up and down in the substrate.
In such a semiconductor device, a gate structure configured to deliver a voltage to the gate is formed on the entire surface of the semiconductor chip. Thus, capacitance is generated between the gate structure and drain on the bottom surface of the substrate. Due to the capacitance that is generated between the gate structure and the drain, reverse capacitance increases, which in turn reduces the switching ability of the entire device.